There is a demand in the semiconductor industry to produce semiconductor wafers with higher device densities. Such high densities require that the dimensions of the device be scaled down requiring smaller and smaller feature sizes. For example, semiconductor wafers are typically composed of different interconnected layers and the width and spacing of interconnecting lines must necessarily be closer and closer together.
Failure of the semiconductor wafer sometimes occurs due to various physical, chemical, or mechanical problems. For example, failure may occur due to electrical overstress, contamination, or wear out. When there is a failure it is important to perform an analysis for to find where and why the device fails. Before fault analysis can be performed the sample must be prepared to isolate and expose the fault for analysis. This process is typically known as fault isolation. The fault isolation process can be performed using known methods, such as, for example, electrical probing and active or passive voltage contrast on uniform surfaces at a target area or the region of the defective circuit or fault. The target area is generally the location believed to be the cause of the failure.
Fault analysis using electrical probing typically includes moving a probe into contact with an electrical circuit on a surface of a sample and applying a voltage or current. One important process in fault isolation using electrical probing includes removing material from the sample surface one layer at a time at or near the target area so that each layer can be sequentially inspected by known voltage contrast methods or probed so that the failure can be isolated and analyzed. It is important to have a clean uniform surface to provide a good electrical or ohmic contact between the probe and the electrical circuit in order to measure the desired electrical property of the circuit. Inspection of the target area can be done using a scanning electron microscope (SEM) or other inspection methods, such as, for example, ion beam imaging. Inspection of the target area typically requires a controlled environment in which the sample is place within a controlled environment, such as, for example, a vacuum chamber.
The process of surface removal by layer is generally referred to as surface delayering. Known methods of delayering are time consuming, difficult, and often result in a sample surface on which it is difficult to perform any fault analysis. Delayering is even more difficult when the target area is located beneath one or more layers and becomes more difficult as the layers become increasingly thinner.
Most current methods of delayering are ex-situ. That is, the methods are performed outside of the SEM vacuum chamber. For example, the sample is removed from the vacuum chamber so that a target area can be polished, etched, or otherwise exposed for inspection, which takes place inside the vacuum chamber. Known methods of surface delayering include mechanical polishing or abrading the sample, wet chemical deprocessing, or dry etch processing (RIE). All of these ex-situ methods require very precise control of every step involved in the process in order to ensure accurate results. Generally, these methods are directed to global delayering or removing layers from the entire sample surface. Additionally, monitoring of the delayering process and target area inspection requires frequent and time-consuming transfer of the sample from the SEM chamber to another location for processing and then transfer back to the SEM chamber for monitoring and inspection. The process is time consuming and requires a high level of skill to produce reliable end results. If the process does not produce the desired results then the process may have to be repeated until the desired results are achieved. Even with the high level of skill involved the process typically produces a non-uniform surface of the sample which interferes with the failure analysis. Furthermore, the process leads to contamination of the target area because of residual debris and/or contaminants, such as, for example, abrasive slurry or chemical products used in the delayering process.
Another known method of surface delayering uses a focused ion beam (FIB). One benefit of FIB delayering is that it is typically conducted in-situ or within the vacuum chamber so that the sample does not have to be removed and taken to another location for processing. In a typical FIB delayering process, a target area is exposed using a focused ion beam. Typical FIB techniques use a low level of current remove an area of material from a wafer surface. Various FIB techniques are known. For example, one FIB technique may use less than about 1,000 picoamperes (pA) to expose a target area of about 15 micron (μm)×15 μm. One problem with this and other FIB techniques is that they are time consuming due to the low level current, which can be on the order of about thirty minutes. Additionally, surface delayering by FIB often results in a non-uniform surface. A non-uniform surface prevents good ohmic contact between the probe and sample surface because the contact between the probe and the electrical circuit is not of sufficient quality and prevents measuring the desired electrical property of the electrical circuit as needed for fault isolation. For example, with FIB delayering the surfaces of the sample structure often consist of different materials and typically contain copper structures. The various materials have different mill rates which can be one cause of non-uniformity of the delayered surface. Another cause of non-uniform surfaces is that the copper structures are typically polycrystalline with some grain oriented in channeling directions. Once a non-uniform surface is created, further delayering exacerbates the surface non-conformity, especially for the layer where no inherent etch stop layer exists. One example of an undesirable non-uniform sample surface resulting from FIB delayering is shown in FIG. 1. A sample 100 is shown with a region 102 exposing a delayered surface 104. Here, it can be seen that the delayered surface 104 of the sample 100 is non-uniform in depth exposing some electrical circuitry while other circuitry is etched away or is unreachable by the probe. This results in a sample that is not useful for fault isolation.
Other in-situ work piece processing methods are known, such as, for example, repair of defects in lithographic photo-masks and semiconductors. One such method is shown in described in U.S. Pat. No. 7,375,324, to Linder et al, for “Stylus System for Modifying Small Structures.” This method repairs defects of the type that lie above the sample surface. In this method, a probe having a cross section of about 0.2 μm or less is scanned horizontally across the surface of a sample. At various locations, the probe is stopped and lowered until it contacts the sample surface. The height at which the probe tip stops is measured by circuitry. The probe tip is then retracted and moved to another predetermined location at which the height is again measured. A series of such measurements are conducted to provide a profile or topography of the sample to locate the defect. Once the defect is located, the probe tip is brought into contact with the defect material and the probe tip is moved in a back-and-forth manner called dithering to cause small fractures in the defect material which breaks up the defect into fragments that are then pushed away from the upper surface of the sample. However, this method and apparatus is used for repairing defects and is not capable of delayering a sample surface for fault analysis.
What is needed is an apparatus and method that overcomes the problems of prior known methods of preparing a sample for fault analysis by eliminating time consuming ex-situ processing steps. What is also needed is an apparatus and method of preparing a sample for fault analysis that is free of contamination and debris. Furthermore, what is further needed is an apparatus and method that is free of problems of known in-situ processing steps by providing a target area of a sample having a clean and uniform surface.